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HomeProductsIntegrated Circuits (ICs)PMIC - SupervisorsS-80847CNY-Z2-U
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S-80847CNY-Z2-U - ABLIC Inc.

Manufacturer Part Number
S-80847CNY-Z2-U
Manufacturer
ABLIC
Allelco Part Number
98D-S-80847CNY-Z2-U
Warranty
1 Year Allelco Warranty - Find out more
Stock Status:
46,041 pcs available, New & Original
Parts Description
IC SUPERVISOR 1 CHANNEL TO92-3
Package
TO-92-3
Data sheet
S-80847CNY-Z2-U.pdf

HTML Datasheet

S-808xxC Series.pdf
RoHs Status
RoHS Compliant
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In stock: 46041
  • Unit Price: $0.307
  • Subtotal: $0.00

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Quantity Unit Price Ext. Price
1+ $0.307 $0.31
The above prices does not include taxes and freight rates, which will be calculated on the order pages.

Specifications

S-80847CNY-Z2-U Tech Specifications
ABLIC Inc. - S-80847CNY-Z2-U technical specifications, attributes, parameters and parts with similar specifications to ABLIC Inc. - S-80847CNY-Z2-U

Product Attribute Attribute Value
Manufacturer ABLIC
Voltage - Threshold 4.7V
Type Voltage Detector
Supplier Device Package TO-92-3
Series S-808xxC
Reset Timeout -
Reset Active Low
Product Attribute Attribute Value
Package / Case TO-226-3, TO-92-3 (TO-226AA) Formed Leads
Package Tape & Reel (TR)
Output Open Drain or Open Collector
Operating Temperature -40°C ~ 85°C (TA)
Number of Voltages Monitored 1
Mounting Type Through Hole
Base Product Number S-80847

Environmental & Export Classifications

ATTRIBUTE DESCRIPTION
RoHs Status RoHS Compliant
Moisture Sensitivity Level (MSL) 1 (Unlimited)
ECCN EAR99
HTSUS 8542.39.0001

Frequently Asked Questions(FAQ)

What is the typical supply current consumption of the S-80847CNY-Z2-U when operating at room temperature, and how does this influence power budgeting in low-power embedded systems?
The S-80847CNY-Z2-U draws approximately 5 µA under nominal conditions at 25°C, making it suitable for battery-powered applications where quiescent current must remain below 10 µA to extend operational life. This low draw directly reduces standby power dissipation in microcontroller-based designs, enabling longer runtime without compromising reset reliability.
How does the S-80847CNY-Z2-U compare to the S-80846CNY-Z2-A in terms of threshold voltage accuracy and long-term drift, particularly in automotive-grade temperature cycling environments?
While both devices share the same 4.7V nominal threshold, the S-80847CNY-Z2-U offers ±2% initial accuracy versus the S-80846’s ±3%, resulting in tighter voltage monitoring precision. Over a -40°C to +85°C range, the S-80847 exhibits less than 1% total variation due to improved internal bandgap reference stability, which is critical in systems requiring consistent brown-out detection across industrial temperature swings.
Can the S-80847CNY-Z2-U be used as a substitute for a dedicated reset IC in a 3.3V microcontroller system with a regulated 5V input, and what modifications are necessary?
No direct substitution is recommended without design adjustments. Although its 4.7V threshold exceeds standard 3.3V logic levels, it can monitor a 5V rail and generate an active-low reset signal compatible with 3.3V microcontrollers via level shifting. However, users must ensure the open-drain output pulls down sufficiently fast relative to the MCU’s reset pin capacitance, typically requiring a pull-up resistor no greater than 10 kΩ to maintain valid timing margins.
In a multi-supervisor architecture, how should multiple S-80847CNY-Z2-U units be daisy-chained or coordinated to avoid race conditions during power-up sequencing?
Daisy-chaining is not supported due to the open-drain output structure; instead, each supervisor should monitor a distinct rail or node. For shared monitoring points, use diodes with forward voltage drops matched within 10 mV to combine signals safely. Alternatively, connect outputs to a wired-OR configuration using a single pull-up resistor, ensuring all devices have matched thresholds to prevent one from masking another during transient events.
What external components are required for reliable operation of the S-80847CNY-Z2-U, and how do they affect response time and noise immunity?
Only a pull-up resistor is needed on the open-drain output, typically between 1 kΩ and 10 kΩ. A smaller resistor improves rise time but increases power consumption; a larger value enhances noise immunity but risks slow assertion during deep discharges. No external capacitors are required for internal hysteresis, though adding a 0.1 µF bypass capacitor near the VCC pin improves transient rejection by suppressing high-frequency switching noise.
Is it acceptable to operate the S-80847CNY-Z2-U outside its specified operating temperature range, and what degradation mechanisms occur at elevated temperatures above 85°C?
Operation beyond 85°C violates datasheet specifications and risks parametric drift. At sustained temperatures above this limit, the internal bandgap reference may exhibit increased offset, causing threshold inaccuracy exceeding ±5%. Additionally, leakage currents rise significantly, potentially triggering false resets even when the supply voltage remains within tolerance.
How does the S-80847CNY-Z2-U handle undervoltage lockout (UVLO) behavior during rapid power cycling, and what minimum hold-up time ensures reliable reset release?
The device features built-in hysteresis to prevent chatter during marginal supply conditions. With a typical hysteresis width of 100 mV around the 4.7V threshold, a stable reset deassertion requires the supply voltage to remain above 4.8V for at least 10 ms after crossing the upper threshold. Below this duration, the output may oscillate or fail to release properly.
Can the S-80847CNY-Z2-U monitor a battery voltage while powered from the same source, and what precautions prevent feedback coupling?
Yes, it can monitor a secondary battery branch through a resistive divider, but isolation is essential. Use separate traces or ground planes to avoid feedback from the supervisor’s own power rail. If co-located, add a small series inductor (e.g., 10 µH) between the monitored node and the divider network to dampen high-frequency coupling from digital switching noise.
What is the maximum allowable load capacitance on the reset output line of the S-80847CNY-Z2-U, and how does this impact PCB layout decisions?
The open-drain driver can source/sink up to 1 mA, limiting effective drive strength. With a 10 kΩ pull-up, the RC time constant should stay under 1 ms to meet typical MCU reset timing requirements. Therefore, total stray capacitance—including trace parasitics and input capacitance of downstream devices—must remain below 100 pF. Keep output traces short and avoid vias to minimize capacitance accumulation.
Does the S-80847CNY-Z2-U support manual reset functionality, and if so, how is this implemented without additional components?
No native manual reset feature exists. However, a momentary switch can be connected between the reset output and ground, creating an active-low override. When pressed, the switch pulls the line low regardless of the internal state, simulating hardware reset. Ensure debouncing is handled externally or in firmware to avoid spurious triggers.
How does the S-80847CNY-Z2-U perform in noisy industrial environments with fast voltage transients, and what design mitigations improve robustness?
The device includes transient rejection circuitry capable of tolerating ±1V spikes up to 100 ns wide without triggering false resets. For stronger transients, place a TVS diode rated for 6V clamping voltage close to the VCC pin and ensure adequate decoupling. Layout symmetry and star grounding also reduce susceptibility to common-mode disturbances.
What is the recommended storage condition for unmounted S-80847CNY-Z2-U devices prior to assembly, and how does moisture sensitivity affect lead integrity during reflow?
Store in dry ambient conditions (<40% RH) at ≤30°C to prevent tin whisker growth. As an MSL 1 component, it has unlimited floor life, but prolonged exposure to humid environments (>60% RH) can cause oxidation on leads, increasing contact resistance during soldering. Always inspect leads before placement if stored beyond six months.
Can the S-80847CNY-Z2-U be used in redundant power architectures where two supplies must agree before system enablement, and how is voting logic implemented?
Yes, but only if both supplies are monitored independently. Connect each S-80847CNY-Z2-U to its respective rail, then combine their open-drain outputs via a wired-AND configuration using a common pull-up. System reset is valid only when both supervisors assert low, ensuring neither rail drops below 4.7V simultaneously. This requires careful matching of thresholds and response times to avoid latency mismatches.
How does the S-80847CNY-Z2-U compare to ceramic resonator-based clock monitors in terms of cost, footprint, and functional scope?
Unlike clock monitors that track oscillator integrity, the S-80847CNY-Z2-U provides pure voltage supervision without requiring external timing elements. It occupies a smaller footprint (TO-92-3 vs. SOT-23 or QFN packages) and consumes far less power, making it ideal for simple power-fail detection. However, it cannot detect clock failure modes like drift or stoppage, so complementary monitoring strategies are often needed for comprehensive system health management.

Parts with Similar Specifications

The three parts on the right have similar specifications to ABLIC Inc. S-80847CNY-Z2-U

Product Attribute S-80847CNY-B2-U S-80847CNMC-B88T2U S-80847CNUA-B88T2U S-80847CNY-B-G
Part Number S-80847CNY-B2-U S-80847CNMC-B88T2U S-80847CNUA-B88T2U S-80847CNY-B-G
Manufacturer ABLIC Inc. ABLIC Inc. ABLIC Inc. ABLIC Inc.
Mounting Type - Surface Mount Through Hole Surface Mount
Reset Timeout - - - -
Type - - - -
Base Product Number - DAC34H84 MAX500 ADS62P42
Package / Case - 196-LFBGA 16-DIP (0.300', 7.62mm) 64-VFQFN Exposed Pad
Series - - - -
Operating Temperature - -40°C ~ 85°C 0°C ~ 70°C -40°C ~ 85°C
Supplier Device Package - 196-NFBGA (12x12) 16-PDIP 64-VQFN (9x9)
Output - - - -
Voltage - Threshold - - - -
Package - Tape & Reel (TR) Tube Tape & Reel (TR)
Reset - - - -
Number of Voltages Monitored - - - -

S-80847CNY-Z2-U Datasheet PDF

Download S-80847CNY-Z2-U pdf datasheets and ABLIC Inc. documentation for S-80847CNY-Z2-U - ABLIC Inc..

PCN Design/Specification
Solder Plating Material Chg 10/Dec/2018.pdf All Dev Materials Chg 23/Mar/2020.pdf
HTML Datasheet
S-808xxC Series.pdf

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Shipment

Delivery Time

In-stock items can be shipped within 24 hours. Some parts will be arranged for delivery within 1-2 days from the date all items arrive at our warehouse. And Allelco ships order once a day at about 17:00, except Sunday. Once the goods are shipped, the estimated delivery time depends on the shipping methods and Delivery destination. The table below shows are the logistic time for some common countries.

Delivery Cost

  1. Use your express account for shipment if you have one.
  2. Use our account for the shipment. Refer to the table below for the approximate charges.
(Different time frame / countries / package size has different price.)

Delivery Method

  1. Global Common Shipment by DHL / UPS / FedEx / TNT / EMS / SF we support.
  2. Others more shipping ways, please get in touch with your customer manager.

Common Countries Logistic Time Reference
Region Country Logistic Time(Day)
America United States 5
Brazil 7
Europe Germany 5
United Kingdom 4
Italy 5
Oceania Australia 6
New Zealand 5
Asia India 4
Japan 4
Middle East Israel 6
DHL & FedEx Shipment Charges Reference
Shipment charges(KG) Reference DHL(USD$)
0.00kg-1.00kg USD$30.00 - USD$60.00
1.00kg-2.00kg USD$40.00 - USD$80.00
2.00kg-3.00kg USD$50.00 - USD$100.00
Note:
The above table is for reference only. There may have some data bias for the uncontrollable factors.
Contact us if you have any questions.
  • QC (Quality Warranty)
  • Payment Support
  • Packaging
  • Certifications & Memberships

QC (Quality Warranty)

Allelco is committed to exceeding customer expectations through customer service excellence, order accuracy, and on-time delivery.
This is achieved through our commitment to the continual improvement of our processes, services, and products.


Strict quality inspection builds a solid foundation for electronic component quality.
  1. Visual inspection
  2. Performance testing and reliability verification
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We eliminate defective components and ensure the stable operation of electronic devices through professional quality standards.
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Packaging

Electrostatic Discharge Protection and Handling

All electrostatic-sensitive components are handled in accordance with electrostatic discharge control procedures. The products are hermetically sealed in anti-static safe packaging to prevent electrostatic damage. Appropriate labeling is also applied for identification and traceability. This ensures product integrity during storage, handling and transportation.


ESD

Certifications & Memberships

Third-party certified, strict quality control. Our certification
  • ISO 9001: 2015
  • ISO 13485: 2016
  • ISO 14001: 2015
  • ISO 28000: 2007
  • ISO 45001: 2018
  • GB/T 27922-2011
  • SMTA
  • IPC
  • ESD
  • PSMA
S-80847CNY-Z2-U Image

S-80847CNY-Z2-U

ABLIC Inc.
98D-S-80847CNY-Z2-U

Want a better price? Add to Cart and Submit RFQ now, we'll contact you immediately.

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