on December 30th 3,094

Erasable Programmable Logic Devices (EPLDs): A Guide to Design and Applications

This guide introduces Erasable Programmable Logic Devices (EPLDs), a flexible and reusable technology in integrated circuits. Unlike traditional programmable devices, EPLDs can be reconfigured multiple times, making them ideal for evolving design needs. We’ll explore their capabilities, applications in industries like telecommunications and automotive, and key factors to consider when using these versatile devices in modern electronics.

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Overview

Erasable Programmable Logic Devices (EPLDs), introduced in the mid-1980s by Aitera, revolutionized programmable logic with their high integration density and flexibility, surpassing the capabilities of similar devices like Generic Array Logic (GAL). EPLDs enable a broader range of logic functions within a single chip, making them versatile and efficient for various applications. Their reprogrammability allows to adapt designs without replacing hardware, a key advantage in industries like telecommunications and automotive, where rapid prototyping is needed. EPLDs' compact design and low power consumption make them ideal for embedded systems and portable devices, highlighting their technical and practical advantages in modern digital logic design.

PLD Device Design Steps

Designing a Programmable Logic Device (PLD) involves several steps to create a functional and efficient design.

The process begins with defining the circuit logic functions. This can be done using either schematic diagrams or Hardware Description Languages (HDLs). Schematic diagrams provide a straightforward way to visualize basic logic circuits but are less effective for handling complex designs. In contrast, HDLs offer a more concise and flexible way to describe logic functions, making them the preferred choice for modern PLD designs.

Next, designers choose a suitable HDL for their project. Popular options include ABEL, VHDL, and Verilog. ABEL is ideal for simpler designs, like counters or encoders, because it uses Boolean equations and truth tables. VHDL is more structured and excels in handling complex logic, making it suitable for intricate projects. Verilog, with its compact, C-like syntax, is great for both logic design and simulation, making it a versatile option for advanced applications. The choice of HDL depends on the project's complexity and specific requirements.

Once the logic functions are defined, the next step is programming and simulation. Specialized software compiles the described logic and converts it into Boolean expressions, which are then saved as a JEDEC (JED) file. Before the design is transferred to hardware, simulations are performed within the software to verify that the logic functions as intended. This simulation phase is important, as it ensures the design meets performance specifications and reduces the likelihood of errors during implementation.

Finally, the design is downloaded to the PLD device. This involves transferring the JEDEC file to the hardware using a programmer, a device specifically designed to write the file into PLDs such as PROMs, EEPROMs, GALs, CPLDs, or PALs. Programmers connect to a computer via a parallel port and accurately load the design onto the hardware. This step completes the process, transforming the design from a digital model into a physical, functioning device.

The PLD design process involves four main steps: defining the logic functions, choosing an appropriate HDL, programming and simulating the design, and downloading the final design to the hardware. Each stage plays a role in ensuring the success and reliability of the device. As tools and methods continue to evolve, PLD designs are becoming more flexible, efficient, and capable of handling increasingly complex applications.