on July 24th 24,773

Understanding Gated SR Latches: Truth Table, Circuits and Working Principle

A gated SR latch is a simple circuit that stores one bit of data. It works only when an enable or clock signal is on, making it more reliable than a basic SR latch. This article explains how it works, how it is built with logic gates, its symbol and truth table, its timing, its use in PLCs, how it differs from a basic SR latch, where it is used, and its pros and cons.

Catalog

Figure 1. Gated SR Latch

What is a Gated SR Latch?

A gated SR latch, also called a clocked or synchronous SR latch, is an improved version of the basic SR latch that includes an enable signal (or clock/control input). The output changes only when this enable signal is active, allowing updates to occur in a controlled and timed manner.

This design prevents the unpredictable behavior often seen in simple SR latches, which react immediately to input changes without timing control. By using the enable signal as a gate, the latch synchronizes both data storage and retrieval.

Gated SR Latch Circuits

Gated SR Latch Using NOR and AND Gates

Figure 2. Gated SR Latch Using NOR and AND Gates

This design stores one bit of data using a combination of AND and NOR gates. The circuit includes three inputs: Set (S), Reset (R), and Clock (Clk). It produces two complementary outputs, Q and Q̅, representing the stored value and its inverse.

The AND gates act as filters. They allow the Set and Reset inputs to reach the NOR-based memory core only when Clk is high (logic 1). When Clk is low, the AND gates block any changes, and the latch holds its previous state.

The cross-coupled NOR gates form a feedback loop, which is the core memory element. This loop ensures that the circuit “remembers” its current state until a new valid input overrides it.

Operation of NOR-AND Latch:

• Set condition: S = 1, R = 0, Clk = 1 → Q is forced to 1 (latch stores a high).

• Reset condition: R = 1, S = 0, Clk = 1 → Q is forced to 0 (latch stores a low).

• Hold condition: S = 0, R = 0, Clk = 1 → Q keeps its previous value (no change).

• Invalid condition: S = 1, R = 1 → Q enters an undefined state (must be avoided).

Gated SR Latch Using NAND Gates

Figure 3. Gated SR Latch Using NAND Gates

A NAND-based gated SR latch works on the same principle but replaces NOR logic with NAND logic. It still has S, R, and Clk inputs and produces complementary outputs Q and Q̅.

The NAND gates ensure that Set and Reset can modify the state only when Clk is active (high). The cross-coupled NAND gates then lock the output into its last state, similar to the NOR version.

Operation of NAND-Based Latch:

• Set condition: S = 1, R = 0, Clk = 1 → Q = 1.

• Reset condition: R = 1, S = 0, Clk = 1 → Q = 0.

• Hold condition: S = 0, R = 0, Clk = 1 → Q retains its current state.

• Invalid condition: S = 1, R = 1 → Q becomes undefined.

Symbol of a Gated SR Latch

Figure 4. Symbol of a Gated SR Latch

The symbol for a gated SR latch shows three inputs: Set (S), Reset (R), and Enable (E), and two outputs, Q and Q̅. The behavior is simple. When E is high, the latch responds to S and R inputs. When E is low, the latch ignores input changes and keeps its current output.

Gated SR Latch Truth Table

Enable (E)	Set (S)	Reset (R)	Next Q	Description
0	X	X	Q	Latch disabled
1	0	0	Q	Hold state
1	1	0	1	Set state
1	0	1	0	Reset state
1	1	1	–	Undefined state

When E = 0, the latch does nothing. Q simply holds whatever value it had before.

Timing Diagram of a Gated SR Latch

Figure 5. Timing Diagram of a Gated SR Latch

A timing diagram illustrates how a latch or flip-flop responds to its input signals (in this case, S, R, and Clk) over time. For a Gated SR Latch, the clock signal (Clk) controls when the outputs Q and Qˉ are allowed to change.

1. At t1:

The clock signal Clk = 1, and the set input S = 0. With R = 1 (reset active), the latch is reset, and Q = 0 while Qˉ=1.

2. At t2:

S switches to 1 while Clk is still 1. This activates the set condition, causing Q to switch to 1 and Qˉ to 0.

3. At t3:

The clock drops to 0. At this point, the latch is “frozen,” meaning Q and Qˉ hold their current values regardless of changes in S or R. The gated latch updates outputs only when Clk = 1.

4. At t4:

Clk rises back to 1, and the outputs Q and Qˉ again respond to the current states of S and R. For example, if R = 1 and S = 0, Q will reset to 0.

Gated SR Latch in Ladder Logic

Figure 6. Gated SR Latch in Ladder Logic

In programmable logic controllers (PLCs), latching circuits are important for memory functions. A gated SR latch can be implemented using ladder logic diagrams, as shown above.

In this circuit:

• CR1 acts as the Set relay (S).

When both Enable (E) and S are active (logic high), CR1 energizes, setting the output Q to high (1).

• CR2 acts as the Reset relay (R).

When both E and R are active, CR2 energizes, which resets Q to low (0).

• Enable (E) acts as a gate signal, ensuring that the latch responds to S or R only when E is high.

When E is low, no state change occurs, and Q retains its previous state (it "latches").

Difference Between Gated SR Latch and Basic SR Latch

Aspect	Basic SR Latch	Gated SR Latch
Control Signal	No Enable input; directly controlled by S and R.	Includes an Enable (E) input to control operation.
Response	Output changes immediately with S or R input.	Output changes only when Enable (E) is active.
Synchronization	Operates asynchronously.	Operates synchronously with Enable signal.
Timing Control	No specific timing control.	Timing is regulated by Enable or clock signals.
Glitch Prevention	Susceptible to unwanted state changes.	Reduces glitches by requiring Enable to be high.
Design Complexity	Simple structure with just NOR or NAND gates.	Slightly more complex due to additional control input.
Output Stability	Output may change unexpectedly when inputs vary.	Output remains stable when Enable is low.
Suitability for Flip-Flops	Not ideal for clocked flip-flop design.	Used as a basis for creating clocked flip-flops.
Applications	Small logic circuits and simple memory storage.	Sequential logic, memory units, and clocked systems.
Power Consumption	Slightly lower due to fewer gates.	Slightly higher due to the additional control logic.

Gated SR Latch Advantages and Limitations

Advantages

• Controlled and predictable state changes, making it reliable for binary storage.

• Simple design that requires only a few basic logic gates.

• Easily integrates with synchronous circuits as a building block.

• Low hardware cost due to minimal gate requirements.

• Fast response time because outputs change quickly with inputs (limited by gate delay).

• Serves as the foundation for building flip-flops, registers, and memory systems.

• Easy to understand conceptually, making it ideal for learning about sequential circuits.

Limitations

• Undefined or invalid behavior when both S and R inputs are high.

• Sensitive to input glitches or noise due to level-triggered nature.

• Requires additional logic in complex designs to prevent invalid input conditions.

• Less reliable for precise timing in high-speed systems compared to edge-triggered flip-flops.

• Limited functionality on its own, cannot store more than one bit without additional components.

• Risk of race conditions if inputs change simultaneously or very close together.

Conclusion

A gated SR latch is an important part of digital circuits because it stores data in a safe and controlled way. It is useful for avoiding glitches, matching signals with clock timing, and building more complex circuits like flip-flops and memory units. Its design is simple and works well for tasks like holding data, cleaning signals, and keeping control signals active. However, it can have problems if both set and reset inputs are active at the same time, and it can be sensitive to noise. It also stores only one bit of data, so it needs extra parts for bigger or faster systems.